Senior Staff Mixed Signal IP Enablement and Debug Engineer

Job Details:Job Description: About the RoleJoin Intel's Hard IP Development Group (HIPD) within the Central Engineering Organization, where innovation meets execution. Our team develops industry-leading intellectual property that powers high-performance products across Server, Client, and Networking SoCs, as well as solutions for Intel Foundry customers.HIPD creates a comprehensive portfolio of cutting-edge Mixed Signal IPs including general purpose IOs, Digital Thermal Sensors, PLLs, Serial and Parallel IO PHYs (DDR/LPDDR, PCIe, USB, Type-C, UCIe Die-to-Die), and Ethernet PHYs. As part of our IO Post Silicon Validation Debug team, you'll work with a dynamic group of engineers who serve as the critical bridge between IP design teams and SoC customers throughout the validation and debug process.Key ResponsibilitiesCustomer-Focused IP EnablementProvide Response for IP Questions to customers timelyProvide IP reviews, Lab Demos, and Training to customers as neededGenerate Industry standard IP documentations and collaterals as needed for external customersPartner closely with SoC customers and IP design teams to deliver comprehensive pre-silicon to post-silicon IP Integration and Debug supportDevelop and execute test plans and content using AI-driven tools and Python/System Verilog scriptingConduct SoC board design reviews and provide technical recommendationsPerform signal integrity and power integrity simulations to optimize design performanceSilicon Validation & Debug LeadershipServe as the IP team representative during SoC power-on activities for test chips and productsProvide hands-on IP enabling support throughout the silicon bring-up processLead identification, investigation, and resolution of IP-related silicon issuesExecute timely debugging and disposition of customer issues and sightingsTechnical Problem SolvingConduct both pre-silicon and post-silicon issue reproduction and analysisDrive root cause analysis initiatives with comprehensive failure analysisCollaborate across cross-functional teams to deliver robust solutionsMaintain customer obsession by ensuring rapid resolution of IP-related challengesCore CompetenciesAble to work independently with design team and customers to solve issues either remotely or onsite.Able to lead on IP debug as situation arises in addition to hands on debugQualifications:The Minimum qualifications are required to be initially considered for this position.  Minimum qualifications listed below would be obtained through a combination of industry relevant job experience, internship experience and / or schoolwork/classes/research. The preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.Minimum QualificationsBachelors and 7+ years of experience or Masters degree and 4+ years of experience in Computer Engineering, Electrical Engineering, or in a related fieldExperience in IP Integration, pre-silicon verification, Electrical or Functional Post Silicon validation and debug with either serial IOs (PCIe, USB, SATA, TypeC, Ethernet) or parallel IOs (DDR, LPDDR, UCIe Die2Die)2+ years of experience with the lab hardware and softwareExperience using Oscilloscopes, Logic Analyzers, Protocol analyzers and BERTs (Bit Error Ratio Testers)Experience with at least one or more industry standard IO specifications like DDR, LPDDR, PCIE, USB, USB TypeC, Die2Die, Ethernet, etc. Either PHY or Controller experience is goodPreferred Qualifications Ph.D. degree in Computer Engineering, Electrical Engineering, or in a related fieldExperience in signal integrity, power delivery, IBIS-AMI model development and silicon co- relationPre-silicon design or simulation experience in logic, circuits, firmware or MRC and mixed signal validationWhy This Role MattersYou'll play a pivotal role in ensuring Intel's IP portfolio meets the demanding requirements of next-generation computing platforms. Your work will directly impact product success across multiple market segments while advancing the state-of-the-art in high-speed IO technologiesThis position offers the unique opportunity to work at the intersection of cutting-edge IP development and real-world customer applications, making you an integral part of Intel's continued innovation leadership          Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, FolsomAdditional Locations:US, California, Santa ClaraBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.   Annual Salary Range for jobs which could be performed in the US: $164,470.00-311,890.00 USD  The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and add