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Principal FPGA Engineer

at Collins Aerospace

Collins AerospaceUS-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150APosted 2026-06-24
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Job description

Date Posted:2026-06-24 Country:United States of America Location:US-IN-FT WAYNE-150A ~ 1010 Production Rd ~ BLDG 150A Position Role Type:Onsite U.S. Citizen, U.S. Person, or Immigration Status Requirements: The ability to obtain and maintain a U.S. government issued security clearance is required.​ U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance Security Clearance Type: DoD Clearance: Secret Security Clearance Status: Active and existing security clearance required after day 1At Raytheon, the foundation of everything we do is rooted in our values and a higher calling – to help our nation and allies defend freedoms and deter aggression. We bring the strength of more than 100 years of experience and renowned engineering expertise to meet the needs of today’s mission and stay ahead of tomorrow’s threat. Our team solves tough, meaningful problems that create a safer, more secure world.The Multi-Product Power & Digital (MPD) department designs FPGAs, circuit cards, and electronics subassemblies for a range of products including missiles/effectors, radars, and electronic warfare systems.  The team leverages digital, analog, and power design skills to provide support throughout the product lifecycle from architecture and design through production and sustainment.The MPD department is seeking a Principal FPGA Engineer to join our team. In this role, you will leverage advanced technologies to create cutting-edge solutions for sensor and effector products. You will partner with experienced, multidisciplinary teams to define requirements, develop architectures, execute detailed design and simulations, and perform integration and verification tasks. You will document your designs within the appropriate configuration management tools and provide comprehensive engineering support throughout the product lifecycle.This position is an onsite role, located in Fort Wayne, IN.What You Will DoProvide full lifecycle support of production quality FPGA designs for all major vendors and device families including: AMD (Xilinx), Altera, and Microchip (Microsemi) using tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.Generate FPGA designs for the following applications: gigabit and multigigabit transceiver (MGT) serial interfaces, Radio Frequency (RF) DSP, controls, data links, embedded processing and processor interfaces.Translate system level requirements into FPGA requirementsArchitect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)Lead small teams of FPGA engineers and code in VHDL for reliability and maintainabilityVerify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverageDefine schedules for FPGA tasking and drive execution to the planned budget and schedule.Identify and manage project risks and opportunities.Create complete documentation including requirements, verification plan, and user’s guidesLead medium sized teams to success.Coach, review, and delegate work to junior engineers.Serve as a subject-matter expert within discipline.Lead internal and external technical reviews.Support customer interactions and relations.Contribute to product and technology roadmapsMake improvements to processes, systems or products to enhance overall performanceEngage in personal technical growth and facilitate technical growth in peers and junior engineers.Qualifications You Must HaveTypically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and a minimum of 8 years of prior relevant experienceExperience to include one or more of the following:FPGA/ASIC design (VHDL and/or Verilog coding) or FPGA/ASIC verification (SystemVerilog coding)Experience with AMD (Xilinx), Altera and/or Microchip (Microsemi) devices and with tools such as AMD Vivado, Altera Quartus Prime Pro or Libero.Hands on experience with integration and debug of FPGA/ASIC in a lab environmentExperience with timing closure, clock domain crossing and reset domain crossing analysis, and constraint development.Experience with source code management, design reviews, and code release in a team development environment.Qualifications We PreferOne or more advanced degrees in Electrical Engineering or a related Science, Technology, Engineering, or Mathematics (STEM) major.  A suitable degree may be counted as 2 years of work experience.FPGA/ASIC design experience in one or more of the following areas:Radar processing techniquesImage processing techniques for visual and infrared sensorsEmbedded systems design using ARM, Microblaze, or NIOS processorsGigabit serial interfaces and multi-gigabit transceivers (MGTs)Constrained random verification in UVM using System VerilogVerification utilizing emulation platforms, such as VeloceExperience with High Level Synthesis (HLS)Experience with vector processors and/or GPUsUsing AI to improve FPGA workflows (verification automation, log triage, regression analytics)AI/ML inference on FPGA (Vitis AI, FINN, custom accelerators)Demonstrated ability to lead successful teams.Experience managing technical, cost, and schedule risks and opportunities.Experience with project management tools such as Earned Value and/or Agile Execution.Experience communicating and documenting technical topics and presenting to customers and management.Experience leading a program transition from development to production.Proposal development experience.Experience with intellectual property generation (patents & publications).Demonstrated mentorship of junior engineers.What We OfferOur values drive our actions, behaviors, and performance with a vision for a safer, more connected world. At RTX we value: Trust, Respect, Accountability, Collaboration, and Innovation.This position offers relocation based on candidate eligibility.Learn More & Apply Now!This position requires a security clearance. DCSA Consolidated Adjudication Services (DCSA CAS), an agency of the
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