Collateral Device Engineer

Job Details:Job Description: About the RoleAre you a passionate device technologist ready to shape the future of semiconductor manufacturing? Join Intel's Manufacturing Development and Customer Engineering (MDCE) organization, where cutting-edge technology meets real-world scalability. In this role, you will sit at the intersection of innovation and execution, playing a critical part in bridging advanced technology development with practical, high-volume manufacturing solutions. If you thrive in a fast-paced, collaborative environment and are driven to solve complex challenges that impact global technology markets, this is the opportunity for you.About the OrganizationThe Manufacturing Development and Customer Engineering (MDCE) organization serves as the bridge between advanced technology development and practical, scalable manufacturing, ensuring that innovative solutions can be successfully produced and delivered to foundry customers. The MDCE Device organization is seeking a highly skilled and experienced device technologist with expertise in device collateral development and design rule implementation for foundry technology development.Position OverviewAs a Collateral Device Engineer, you will be responsible for developing device collateral including test chip designs, DTCO, product scribe line layouts, managing OPC/Mask requests, and overseeing design rules and waivers for technologies currently in large-volume manufacturing. This role focuses on general-purpose logic CMOS technologies to support a broad spectrum of products and markets, including:High-Performance ComputeMobileMixed SignalMemory ControllersDiverse emerging applicationsKey Responsibilities Design and develop comprehensive device collateral including test chip architectures and product scribe line layouts to support technology characterization and monitoringCollaborate with Technology Development teams to establish and refine design rules for newly developed device architectures and customize collateral to meet customer-specific requirementsDevelop and manage design-rule waiver processes, ensuring proper documentation and risk assessment for customer applicationsCreate and optimize scribe line monitoring structures for yield enhancement and process control in high-volume manufacturingWork with manufacturing teams to implement device collateral that meets specifications, yield targets, and provides robust process monitoring capabilitiesDrive the development of standardized test chip methodologies and scribe line layouts compatible with Intel's existing manufacturing processes and platformsAnalyze device parametric data from test chips and scribe line structures to drive continuous improvement in device performance and manufacturabilityProvide technical guidance on design rule compliance and waiver justifications to cross-functional teams and customersStay current with industry trends in device collateral design, test methodologies, and design rule evolution to inform development strategiesQualifications:Minimum QualificationsMaster's degree in Electrical Engineering, Physics, or related field with 7+ years of experience in CMOS device engineering with a focus on test chip design and device collateral developmentExperience in the following:CMOS semiconductor device physics and test chip design for advanced transistor device architectureScribe line layout design and process monitoring structure developmentDesign rule development, validation, and waiver management processesDTCO skills, including SRAM, Standard Cells, and ability to serve as the key interface and bridge between Process Integration, Yield, Device, and Design teamsPreferred QualificationsPh.D. in Electrical Engineering, Physics, or related field with 5+ years of experience in CMOS device engineering and collateral developmentHands-on experience in advanced node test chip design and scribe line optimization for 3nm–16nm FinFETs and sub-3nm GAA FETsExperience in the following:Design Rule Checker (DRC) development and physical verification flowsExperience in a High-Volume Manufacturing environment with a focus on yield monitoring and process control structuresStatistical Process Control (SPC) and advanced data analytics for device collateral optimizationMask generation including Boolean/OPC          Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, California, Santa ClaraAdditional Locations:US, Arizona, Phoenix, US, Oregon, HillsboroBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefitsWe offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at In